1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a control method of a source voltage of a memory cell.
2. Description of the Related Art
FIG. 1 is a configuration of a conventional semiconductor device. A cell array portion 100 composed of multiple memory cells MC includes the memory cells MC at intersections at which word lines WL intersect with bit lines BL. A gate of each memory cell MC is connected to a word line WL, and a drain terminal is connected to the bit line BL. The cell array portion 100 shown in FIG. 1 denotes one sector, which is a unit of reading, programming, or erasing data. A source terminal of the memory cell MC in the same sector is connected to a common source line ARVSS.
The memory cell MC retains a state of data “1” in which a floating gate is not charged and another state of data “0” in which the floating gate is charged. A threshold voltage is low at the data “1”, and the threshold voltage is high at the data “0”.
When the data is read, a given voltage is applied to the word line WL, an n-type MOS transistor (hereinafter, referred to as nMOS transistor) 104 shown in FIG. 1 is turned on, and the source line ARVSS is set to a ground voltage. Thus, the stored data is read according to the difference in the two states of the drain current. Also, when the data is written, a high voltage of approximately 6 V is applied to the bit line BL connected to the selected memory cell MC to be written, and a high voltage of approximately 10 V is applied to the word line WL so that a hot electron generated by flowing the current through the cell may be injected into the floating gate. 0 V is applied to the word line that is not selected so that the unselected memory cell may not be conducted.
However, even if the word line of the unselected memory cell MC is controlled at 0 V, the unselected memory cell MC turns on in some cases. The high voltage is applied to the bit line BL of the selected memory cell. A coupling effect of the drain lines of the selected memory cell and the unselected memory cell connected to the bit line BL boosts the voltage of the floating gate of the unselected memory cell MC, and accordingly the unselected memory cell MC turns on. Then, a leakage current flows through the bit line BL from the unselected memory cell MC. The voltage drop in the parasitic resistance of the bit line BL drops the drain voltage of the selected memory cell MC. The source-drain voltage becomes insufficient and there arises a problem in the program operation.
A control method is employed for setting the voltage of the source line ARVSS at the time of programming to be slightly higher than the ground voltage in order to prevent the problem in the programming operation. That is, an nMOS transistor 103 is turned on by a program signal (PGM) when the data is written and a programming current is passed through a resistor 105 provided between the source line ARVSS and the ground so that the source line ARVSS may have the voltage slightly higher than the ground voltage Vss. When the data is not written, an nMOS transistor 104 is turned on so that the voltage of the source line may be controlled to the ground voltage Vss.
Patent Document 1 (Japanese Patent Application Publication No. 2003-123493) describes that the source voltage of the selected cell transistor is changed according to the distance between the selected cell transistor and the program voltage generation circuit that makes the bit line at a high voltage.
These days the semiconductor device is designed to have a large capacity, and accordingly the cell array region is larger than ever. When the cell array region becomes larger, the resistances of the bit line and the source line become too large to be ignored. At the same time, the programming period into the memory cell is designed to be shorter, and the pulse width for programming is configured as small as possible.
Therefore, even if the source line having a large load is charged in a short period of time, the voltage of the source line is insufficient. There arises a problem in that the programming efficiency is degraded due to the leakage current. Patent Document 1 does not describe the aforementioned technical problem.
In the method of biasing the source line by providing the resistor between the source line and the ground, the degree of the voltage drop to the ground varies depending on the position of the cell to be programmed, and the value of the current is not constant at the time of programming. It is difficult to control the voltage of the source line accurately at a constant level.